Reprints from my posting to SAN-Tech Mailing List and ...


[san-tech][02353] Re: Intel Larrabee路線変更

Date: Tue, 01 Jun 2010 17:30:55 +0900
[san-tech][02860] Intel Many Integrated Core (MIC) at SC '10 (Re: Intel Larrabee路線変更)
[san-tech][02520] Re: Intel Larrabee路線変更
[san-tech][02332] Intel Larrabee路線変更
[san-tech][02352] Re: Intel Larrabee路線変更

この件についての The Registerの記事を流し読みして、とても重要な点を

"Intel puts x64 in a parallel universe", 1st June 2010

No GPU speak required (2ページ冒頭)

  "The important thing about MIC, as far as Intel is concerned, is
   that the same C, C++, and Fortran compilers and the same developer
   tools and libraries used by HPC customers who deploy parallel
   Xeon server clusters will work on the MIC co-processors. There
   will be different optimizations, of course. But you don't have to
   speak GPU to make these things work"

  "By comparison, a Knights co-processor with 50 cores and running at
   maybe 1.5 GHz could have as much as 2 teraflops of single-precision
   floating point performance. It is unclear if it will be able to
   run double precision calculations with any speed, but such a chip
   supporting 1 teraflops of double precision oomph would be compelling
   to a lot of HPC shops with lots of x64 code."

Kirk Skaugen氏は
  Vice President
  General Manager, Data Center Group
  "Skaugen most recently served as general manager of Intel's Server
   Platforms Group."

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