[san-tech][02352] Re: Intel Larrabee路線変更

Date: Tue, 01 Jun 2010 15:45:22 +0900
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2011/06/12
[san-tech][02860] Intel Many Integrated Core (MIC) at SC '10 (Re: Intel Larrabee路線変更)
[san-tech][02520] Re: Intel Larrabee路線変更
[san-tech][02353] Re: Intel Larrabee路線変更
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[san-tech][02332] Intel Larrabee路線変更

> ISC 2010の Kirk B. Skaugen 氏の Keynote Talk (May 31, 11:50am - 12:30pm)
> "HPC Technology - Scale-Up & Scale-Out"
>  Kirk B. Skaugen
>  Vice President, Intel Architecture Group & General Manager,
>  Data Center Group, Intel, USA
>   http://www.supercomp.de/isc10/Conference/Keynotes/HPC-Technology-Scale-Up-Scale-Out
> で公になるのでしょう。

に関してのプレスリリースです：


"Intel Unveils New Product Plans for High-Performance Computing"
 May 31, 2010
  http://www.intel.com/pressroom/archive/releases/2010/20100531comp.htm

NEWS HIGHLIGHTS
----------------------------------------
 * The first product codenamed "Knights Corner" will target Intel's
   22nm process and use Moore's Law to scale to more than 50 Intel cores.
 * Intel Xeon processors and IntelR Many Integrated Core
   architecture-based products to share common tools, software algorithms
   and programming techniques.
 * Products build upon Intel's history of many-core related research
   including Intel's "Larrabee" program and Single-chip Cloud Computer.
 * The share of the TOP500 list that features Intel processors grows to
   408 systems, nearly 82 percent.
----------------------------------------

  "Intel Corporation announced plans to deliver new products based on
   the Intel Many Integrated Core (MIC) architecture that will create
   platforms running at trillions of calculations per second, while
   also retaining the benefits of standard Intel processors."

講演資料 (PDF 7.6MB)
"Petascale to Exascale Extending Intel's HPC Commitment"
 Kirk Skaugen, Vice President, Intel Corporation
 General Manager, Data Center Group
  http://download.intel.com/pressroom/archive/reference/ISC_2010_Skaugen_keynote.pdf

Intel Many Integrated Core (MIC) architectureは 32ページから
※Larrabeeをスッキリさせたものです。
"VECTOR IA CORE" と明記しています。
ただし、メモリコントローラが 1つになっています (Larrabeeは両サイド)。

Intel Many Integrated Core (MIC) architecture-based development card
  http://download.intel.com/pressroom/images/Intel_ISC_2010_Hamburg-KnightsFerry.jpg
(JPG 3.7MB)
Knights Ferry (上記講演資料 34ページ)
  Software development platform
  Growing availability through 2010
  32 cores, 1.2 GHz
  128 threads at 4 threads / core
  8MB shared coherent cache
  1-2GB GDDR5
  Bundled with Intel HPC tools
Software development platform for Intel MIC architecture