[san-tech][02193] Workshop on I/O Virtualization資料公開 (2010/3/13 at ASPLOS 2010)

Date: Wed, 07 Apr 2010 21:16:02 +0900
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 2010年 3月 13日に、ACM ASPLOS 2010 (International Conference on
Architectural Support for Programming Languages and Operating Systems)
の併設ワークショップとして開催された：

Second Workshop on I/O Virtualization (WIOV '10)
  http://sysrun.haifa.il.ibm.com/hrl/wiov2010/index.html
の原稿と発表資料が公開されています：
Workshop Program
  http://sysrun.haifa.il.ibm.com/hrl/wiov2010/program.html



  "SLIM: Network Decongestion for Storage Systems"
  "On Disk I/O Scheduling in Virtual Machines"
  "Ally: OS-Transparent Packet Inspection Using Sequestered Cores"
  "A Network Interface Card Architecture for I/O Virtualization in Embedded Systems"
  "Architectural support for user-level network interfaces in heavily virtualized systems"
  "Enabling Truly Converged Infrastructure", Keynote
  "Redesigning Xen's Memory Sharing Mechanism for Safe and Efficient I/O Virtualization"
  "Power Aware I/O Virtualization" (発表資料無し)
  "I/O Virtualization Bottlenecks in Cloud Computing Today"


他のワークショップ：
EXERT 2010: The Exascale Evaluation and Research Techniques Workshop
  http://www.eecs.umich.edu/exert/
Program
  http://www.eecs.umich.edu/exert/program.html では、例えば、
"Stochastic Queuing Simulation for Data Center Workloads"
 David Meisner and Thomas Wenisch (University of Michigan)
  http://www.eecs.umich.edu/exert/4-exert2010-meisner.pdf

"An FPGA-based Simulator for Datacenter Networks."
 Zhangxi Tan, Krste Asanovic, David Patterson (UC Berkeley)
  http://www.eecs.umich.edu/exert/3-exert2010-tan.pdf
彼等が研究開発中の RAMPを使用しています。
  "We describe an FPGA-based datacenter network simulator for researchers
   to rapidly experiment with O(10,000) node datacenter network
   architectures. Our simulation approach configures the FPGA hardware
   to implement abstract models of key datacenter building blocks,
   including all levels of switches and servers."

  "To reach O(10,000) scale, we plan to put down multiple threaded RAMP
   Gold pipelines in a rack of 10 BEE3 boards as shown in Figure 3.
   Each BEE3 board has four Xilinx Virtex-5 LX155T FPGAs connected with
   a 72-bit wide LVDS ring interconnect. ... resulting in up to 64GB of
   memory for the whole board. Each FPGA provides two CX4 ports, which
   can be used as two 10Gbps Ethernet interfaces to connect multiple
   boards."

  "On each FPGA, we can fit six pipelines to simulate up to 384
   servers. We then can simulate 1,536 servers on one BEE3 board, since
   there are four FPGAs on each board. The onboard 64GB DRAM simulates
   the target memory, with each simulated node having a share of -40 MB."

  "One major datacenter application is running Map-Reduce jobs,"

  "As a proof of concept, we use RAMP Gold to study the TCP Incast
   throughput collapse problem"
   ※[san-tech][01735] TCP Incast関連最新報告～、(2009/06/01)

関連資料：
"Using FPGAs to Simulate Novel Datacenter Network Architectures at Scale"
 Zhangxi Tan, Krste Asanovic, and David Patterson,
 Given on January 2010 at RAMP Retreat, January 2010
  http://ramp.eecs.berkeley.edu/Publications/Using%20FPGAs%20to%20Simulate%20Novel%20Datacenter%20Network%20Architectures%20at%20Scale%20(Slides,%201-29-2010).pptx


U.C. Berkeley Parallel Computing Laboratory, or Par Lab,
  http://parlab.eecs.berkeley.edu/
RAMP - Research Accelerator for Multiple Processors
  http://ramp.eecs.berkeley.edu/


Fifteenth International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS 2010), March 13~17, 2010
  http://www.ece.cmu.edu/~calcm/asplos10/doku.php?id=home
Proceedings at ACM Portal
  http://portal.acm.org/toc.cfm?id=1736020

The 2010 ACM SIGPLAN/SIGOPS International Conference on Virtual Execution
Environments, March 17-19, 2010
  http://vee2010.cs.princeton.edu/Home_Page.html
Final Program
  http://vee2010.cs.princeton.edu/Program.html
Proceedings at ACM Portal
  http://portal.acm.org/toc.cfm?id=1735997

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Date: Thu, 15 Apr 2010 02:10:53 +0900

> EXERT 2010: The Exascale Evaluation and Research Techniques Workshop
>   http://www.eecs.umich.edu/exert/
(中略)
> "An FPGA-based Simulator for Datacenter Networks."
>  Zhangxi Tan, Krste Asanovic, David Patterson (UC Berkeley)
>   http://www.eecs.umich.edu/exert/3-exert2010-tan.pdf
> 彼等が研究開発中の RAMPを使用しています。
(以下略)
について、James Hamilton's Blog: Perspectiveでエントリーがあります

"High Scale Network Research", 2010年4月9日
  http://perspectives.mvdirona.com/2010/04/09/HighScaleNetworkResearch.aspx

  "Zhangxi Tan of Cal Berkeley came up to visit a couple of weeks back.
   I'm interested in Zhangxi's work for two reasons: 1) its based upon
   reconfigurable computing -- a technology ready for commercial application
   and 2) the application of FPGA to network simulation might be a solution
   to the problem of how to test networking gear at credible scale."

※このエントリーの書き出しは
  "High scale network research is hard."
です

"Using FPGAs to Simulate Novel Datacenter Network Architectures at Scale"
 Zhangxi Tan, Krste Asanovic, David Patterson, UC Berkeley
 March 2010
  http://mvdirona.com/jrh/TalksAndPapers/ZhangxiTan_RAMP_IIAB_v2%20.pdf