[san-tech][02121] TRAMS：欧州次世代高信頼性メモリプロジェクト

Date: Sat, 27 Feb 2010 21:07:01 +0900
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欧州の新しいメモリ開発プロジェクトです：

TRAMS : Terascale reliable adaptive memory systems
  http://cordis.europa.eu/fetch?CALLER=PROJ_ICT&ACTION=D&CAT=PROJ&RCN=93073
  Total cost: 3.43 million euro
  Execution: From 2010-01-01 to 2012-12-31 (36 months)

16nm CMOS: Late CMOSや 10nm CMOS; Beyond CMOSをターゲットとしたものの
ようです (でも、3年間の予算)

 "The TRAMS project is the bridge for reliable, energy efficient and
  cost effective computing in the era of nanoscale challenges and
  teraflop opportunities."



 "In order to build reliable nanosystems, the TRAMS project addresses
  a specific variability and reliability-aware analysis and design
  flow as well as a hierarchical tolerance design."
 "The objective of this project is to investigate in depth potential
  new design alternatives and paradigms, which will be able to provide
  reliable memory systems out of highly unreliable nanodevices at a
  reasonable cost and design effort."

当然ながら、信頼性と電力効率ですね。


Project Coordinator: Professor Antonio Rubio
  Department of Electronic Engineering, Campus Nord UPC, SPAIN
Organisations
  INTEL CORPORATION IBERIA S.A., SPAIN
  UNIVERSITY OF GLASGOW, UNITED KINGDOM
  INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW, BELGIUM


"UPC-Barcelona Tech Leads a European Project to Design Memory for
 Future Computers", February 22, 2010
  http://www.upc.edu/eng/noticies/upc-barcelona-tech-leads-a-european-project-to-design-memory-for-future-computers
 "The TRAMS project aims to guarantee that the memory for future
  nanoscale processors, with teraflop capacity, is resilient, reliable,
  fault tolerant, and energy efficient, with advanced features"


"Intel, Glasgow University team up for European memory project". 02/22/2010
  http://www.eetimes.com/news/design/showArticle.jhtml?articleID=223100060
"EU launches TRAMS project for reliable terascale memory systems", 22 February 2010
  http://www.semiconductor-today.com/news_items/2010/FEB/TRAMS_220210.htm
"EU-funded research project launched to investigate on reliable terascale
 memory systems", February 22, 2010
  http://www.nanowerk.com/news/newsid=14980.php
"Glasgow Is Key Team In EU 16nm Tera-Scale Memory Project", 19 February 2010
  http://www.electronicsweekly.com/Articles/2010/02/19/48040/glasgow-is-key-team-in-eu-16nm-tera-scale-memory-project.htm


Professor Antonio Rubioさんのページは見つかりませんでしたが、
Professor Asen Asenov,
Department of Electronics and Electrical Engineering
University of Glasgow
  http://userweb.elec.gla.ac.uk/a/asenov/
Device Modelling Group - University of Glasgow
  http://www.elec.gla.ac.uk/groups/dev_mod/

Intel Spainにもプレスリリースはありませんね。


FP7: FET Proactive Intiative: Concurrent Tera-Device Computing(TERACOMP)
  http://cordis.europa.eu/fp7/ict/fet-proactive/teracomp_en.html
Seventh Framework Programme (FP7)
  http://cordis.europa.eu/fp7/home_en.html