Reprints from my posting to SAN-Tech Mailing List and ...


[san-tech][03205] Video: Kirk Skaugen, Intel at ISC'11 (Re: Intel Many Integrated Core (Intel MIC) Architectureプレスリリース資料等@ISC 2011)

Date: Fri, 24 Jun 2011 00:30:16 +0900

"Intel's 50+ core MIC architecture: HPC on a Card or Massive Co-Processor?"
  April 10, 2012, Dr. Dobbs


"No Free Lunch for Intel MIC (or GPU's)"
 On Apr 3 2012, Steve Scott, NVIDIA Blog

"NVIDIA Pokes Holes in Intel's Manycore Story"
 April 03, 2012, HPCwire

"Nvidia: No magic compilers for HPC coprocessors"
 No free lunch for MIC, either
 3rd April 2012, The Register

"東大のPost T2Kスパコン、IntelのMICの採用を検討"
 2012/02/20, マイナビニュース

[san-tech][03477] Slide: Rice 2012 Oil & Gas HPC Workshop (March 1, 2012)

"Advances in HPC for Oil and Gas: The Intel MIC Architecture"
 Lars Koesterke and Yaakoub El-Khamra
 The University of Texas at Austin


"Justin Rattner氏キーノートスピーチ
 2011年 9月 20日, 【IDF 2011レポート】

キーノートスピーチ Webcast (3件) はこちらで公開されています:
IDF Keynotes

"Intel shows linear scaling with MIC coprocessor"
 Army of Pentiums march in lockstep
 15th September 2011, The Register

"CERN HLT Analysis of Intel Knights Ferry on High Energy Physics"
 2011/07/11, RichReport, 6:05, 1080p

  "In this video, CERN demonstrates performance results from prototype
   Knights Ferry hardware on its high energy physics applications"

"Demo: Linear Speedup on Intel Knights Ferry"
 2011/07/10, RichReport, 2:33, 1080p

  "In this video, Intel demonstrates linear speedups on Knights Ferry on
   Molecular Dynamics"
"Better Together: Intel Demo Shows App Performance Xeon with Knights Ferry"
 2011/07/07, RichReport, 4:15, 1080p

  "In this video, Intel's Chief Software Evangelist James Reinders describes
   the company' Knights Ferry demo at ISC'11."

"Intel MIC architecture for TifaMMy, a Cache-oblivious Matrix-matrix Multiplication"
 2011/07/08, RichReport, 1:33, 1080p

  "In this video, Alexander Heinecke from the Technical University of Munich
   demonstrates the advantages of the Intel MIC architecture for TifaMMy,
   a cache-oblivious Matrix-matrix Multiplication code."

> Presentation:
> "Intel: Accelerating the Path to Exascale"
>  Kirk Skaugen
>  Vice President Intel Architecture Group
>  General Manager Data Center Group

"Intel Press Briefing-- New Exascale Initiative"
 2011/06/22, RichReport, 29:24, 480p

  "At ISC'11, Kirk Skaugen, Intel Corporation vice president and
   general manager of the Data Center Group, outlined the company's
   vision to achieve ExaFLOP/s performance by the end of this decade.
   An ExaFLOP/s is quintillion computer operations per second,
   hundreds times more than today's fastest supercomputers. With
   collaboration partners, Intel aims to deliver complete technology
   solution for exascale performance by the end of the decade."


"Evaluating the Intel MIC Architecture"
 Arndt Bode, Leibniz Supercomputing Centre (lrz), Germany

の発表まで。それに続く SGIに発表は

> SGI CTO Eng Lim Goh博士のビデオ:
> "SGI Picks the Intel MIC Swim Lane for Exascale by 2018"
>  2011/06/20, RichReport, 5:46, 480p
>   "In this video, SGI's Dr. Eng Lim Goh presents the company's plans
>    to use the Intel MIC architecture on the road to Exascale computing
>    by 2018. Recorded at the Intel Exascale briefing at ISC'11 in
>    Hamburg on June 20, 2011."

"Video: Intel Expects to Achieve Exascale Performance Benchmark"
 06.22.2011, insideHPC
[san-tech][02179] Intel 48コアチップ (Single-chip Cloud Computer)
[san-tech][02200] Re: Intel 48コアチップ (Single-chip Cloud Computer) 
[san-tech][02315] Re: Intel 48コアチップ (Single-chip Cloud Computer)
[san-tech][02860] Intel Many Integrated Core (MIC) at SC '10 (Re: Intel Larrabee路線変更) 
[san-tech][02944] Intel Single-chip Cloud Computer (SCC) On-chip Interconnect評価
[san-tech][03066] Intel、3次元トライゲートトランジスタ プレス資料 (PDF) 等
[san-tech][03192] Intel Many Integrated Core (Intel MIC) Architectureプレスリリース資料等@ISC 2011

0 件のコメント: