------------------------------------------------
2012/04/11
"Intel's 50+ core MIC architecture: HPC on a Card or Massive Co-Processor?"
April 10, 2012, Dr. Dobbs
http://drdobbs.com/parallel/232800139
------------------------------------------------
2012/04/06
"No Free Lunch for Intel MIC (or GPU's)"
On Apr 3 2012, Steve Scott, NVIDIA Blog
http://blogs.nvidia.com/2012/04/no-free-lunch-for-intel-mic-or-gpus/
"NVIDIA Pokes Holes in Intel's Manycore Story"
April 03, 2012, HPCwire
http://www.hpcwire.com/hpcwire/2012-04-03/nvidia_pokes_holes_in_intel_s_manycore_story.html
"Nvidia: No magic compilers for HPC coprocessors"
No free lunch for MIC, either
3rd April 2012, The Register
http://www.theregister.co.uk/2012/04/03/nvidia_scott_coprocessor_programming/
-----
"東大のPost T2Kスパコン、IntelのMICの採用を検討"
2012/02/20, マイナビニュース
http://news.mynavi.jp/articles/2012/02/20/post_t2k/index.html
-----
[san-tech][03477] Slide: Rice 2012 Oil & Gas HPC Workshop (March 1, 2012)
"Advances in HPC for Oil and Gas: The Intel MIC Architecture"
Lars Koesterke and Yaakoub El-Khamra
The University of Texas at Austin
http://og-hpc.org/program2012/abstracts2012/#A3
http://oghpc.blogs.rice.edu/files/2011/09/Koesterke-Elkhamra-final.pdf
------------------------------------------------
2011/09/21
"Justin Rattner氏キーノートスピーチ
～メニイコア時代が到来する"
2011年 9月 20日, 【IDF 2011レポート】
http://pc.watch.impress.co.jp/docs/news/event/20110920_478686.html
キーノートスピーチ Webcast (3件) はこちらで公開されています：
IDF Keynotes
http://www.intel.com/idf/keynote-speakers/index.htm
------------------------------------------------
2011/09/19
"Intel shows linear scaling with MIC coprocessor"
Army of Pentiums march in lockstep
15th September 2011, The Register
http://www.theregister.co.uk/2011/09/15/intel_rattner_mic_coprocessor/
------------------------------------------------
2011/07/13
"CERN HLT Analysis of Intel Knights Ferry on High Energy Physics"
2011/07/11, RichReport, 6:05, 1080p
"In this video, CERN demonstrates performance results from prototype
Knights Ferry hardware on its high energy physics applications"------------------------------------------------
2011/07/12
"Demo: Linear Speedup on Intel Knights Ferry"
2011/07/10, RichReport, 2:33, 1080p
"In this video, Intel demonstrates linear speedups on Knights Ferry on
Molecular Dynamics"
------------------------------------------------
以下のプレゼンターションのビデオが公開されています：------------------------------------------------
2011/07/11
"Better Together: Intel Demo Shows App Performance Xeon with Knights Ferry"
2011/07/07, RichReport, 4:15, 1080p
http://www.youtube.com/watch?v=7xM_SSyjXKg
"In this video, Intel's Chief Software Evangelist James Reinders describes
the company' Knights Ferry demo at ISC'11."
"Intel MIC architecture for TifaMMy, a Cache-oblivious Matrix-matrix Multiplication"
2011/07/08, RichReport, 1:33, 1080p
http://www.youtube.com/watch?v=VRjH8HuRrwg
"In this video, Alexander Heinecke from the Technical University of Munich
demonstrates the advantages of the Intel MIC architecture for TifaMMy,
a cache-oblivious Matrix-matrix Multiplication code."
------------------------------------------------
"Better Together: Intel Demo Shows App Performance Xeon with Knights Ferry"
2011/07/07, RichReport, 4:15, 1080p
http://www.youtube.com/watch?v=7xM_SSyjXKg
"In this video, Intel's Chief Software Evangelist James Reinders describes
the company' Knights Ferry demo at ISC'11."
"Intel MIC architecture for TifaMMy, a Cache-oblivious Matrix-matrix Multiplication"
2011/07/08, RichReport, 1:33, 1080p
http://www.youtube.com/watch?v=VRjH8HuRrwg
"In this video, Alexander Heinecke from the Technical University of Munich
demonstrates the advantages of the Intel MIC architecture for TifaMMy,
a cache-oblivious Matrix-matrix Multiplication code."
------------------------------------------------
> Presentation:
> "Intel: Accelerating the Path to Exascale"
> Kirk Skaugen
> Vice President Intel Architecture Group
> General Manager Data Center Group
> http://newsroom.intel.com/servlet/JiveServlet/download/2152-17-5259/Intel_ISC_2011_MIC_Kirk_Skaugen_Presentation.pdf
"Intel Press Briefing-- New Exascale Initiative"
2011/06/22, RichReport, 29:24, 480p
http://www.youtube.com/watch?v=-L7lFAq6UYw
"At ISC'11, Kirk Skaugen, Intel Corporation vice president and
general manager of the Data Center Group, outlined the company's
vision to achieve ExaFLOP/s performance by the end of this decade.
An ExaFLOP/s is quintillion computer operations per second,
hundreds times more than today's fastest supercomputers. With
collaboration partners, Intel aims to deliver complete technology
solution for exascale performance by the end of the decade."
ただし、
"Evaluating the Intel MIC Architecture"
Arndt Bode, Leibniz Supercomputing Centre (lrz), Germany
の発表まで。それに続く SGIに発表は
> SGI CTO Eng Lim Goh博士のビデオ：
>
> "SGI Picks the Intel MIC Swim Lane for Exascale by 2018"
> 2011/06/20, RichReport, 5:46, 480p
> http://www.youtube.com/watch?v=PZVt5ikvo2k
>
> "In this video, SGI's Dr. Eng Lim Goh presents the company's plans
> to use the Intel MIC architecture on the road to Exascale computing
> by 2018. Recorded at the Intel Exascale briefing at ISC'11 in
> Hamburg on June 20, 2011."
"Video: Intel Expects to Achieve Exascale Performance Benchmark"
06.22.2011, insideHPC
http://insidehpc.com/2011/06/22/video-intel-expects-to-achieve-exascale-performance-benchmark/
================================================
[san-tech][02179] Intel 48コアチップ (Single-chip Cloud Computer)
[san-tech][02200] Re: Intel 48コアチップ (Single-chip Cloud Computer)
[san-tech][02315] Re: Intel 48コアチップ (Single-chip Cloud Computer)
[san-tech][02860] Intel Many Integrated Core (MIC) at SC '10 (Re: Intel Larrabee路線変更)
[san-tech][02944] Intel Single-chip Cloud Computer (SCC) On-chip Interconnect評価
[san-tech][03066] Intel、3次元トライゲートトランジスタ プレス資料 (PDF) 等
[san-tech][03192] Intel Many Integrated Core (Intel MIC) Architectureプレスリリース資料等＠ISC 2011
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