[san-tech][02419] "Energy-proportional Datacenter Networks", Google, ISCA '10

Date: Fri, 25 Jun 2010 03:00:27 +0900
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2011/06/09
[san-tech][02443] Re: "Energy-proportional Datacenter Networks", Google, ISCA '10
[san-tech][02503] Re: "Energy-proportional Datacenter Networks", Google, ISCA '10
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2010年 6月 19日～23日に開催された

ACM IEEE International Symposium on Computer Architecture 2010
  http://isca2010.inria.fr/

で、Googleからとっても興味をひかれる (すごい) 発表がされてました：

"Energy Proportional Datacenter Networks"、
 Dennis Abts (Google Inc.), et al.
 The 37th annual international Symposium on Computer Architecture
  http://doi.acm.org/10.1145/1815961.1816004

Google researchサイト：
"Energy-proportional Datacenter Networks"
  http://research.google.com/pubs/pub36255.html

Abstract
  "In this paper we propose several ways to design a high-performance
   datacenter network whose power consumption is more proportional to
   the amount of traffic it is moving --- that is, we propose energy
   proportional datacenter networks."

で、何と、



  "We first show that a flattened butterfly topology itself is
   inherently more power efficient than the other commonly proposed
   topology for high-performance datacenter networks. We then exploit
   the characteristics of modern plesiochronous links to adjust their
   power and performance envelopes dynamically. Using a network simulator,
   driven by both synthetic workloads and production datacenter traces,
   we characterize and understand design tradeoffs, and demonstrate an
   85\% reduction in power --- which approaches the ideal
   energy-proportionality of the network."

いきなり、"flattened butterfly topology" ！


First Authorの Dennis Abts氏
  http://research.google.com/pubs/author36240.html

  "where he is involved in the system architecture and design of
   next-generation large-scale clusters."

  "Prior to joining Google, Dennis was a Sr. Principal Engineer and
   System Architect for Cray Inc. where he was principally involved with
   the architecture and design of several large-scale parallel
   computers over the span of his 10+ year tenure at Cray. Including,
   the Cray XT3 and XT4 (Red Storm), Cray X1, Cray BlackWidow (XT5),
   and next-generation systems sponsored by the DARPA HPCS initiative."

Publicationsを見て頂ければ・・・

ここでの next-generation systemsは、先日 (2010/05/25) XE6として発表
されたもので、新しいネットワークチップ Geminiを搭載するものです。

Cray Gemini Interconnect Chip & Cray XE6 (Re: [san-tech][02329]
講演資料：CUG 2010 - Cray User Group Meeting, (2010/05/24 - 27))
(2010/05/25)

残念ながら Geminiの詳細は公開されていませんが

Cray XE6
  http://www.cray.com/Products/XE/CrayXE6System.aspx
Cray XE6 Brochure
  http://www.cray.com/Assets/PDF/products/xe/CrayXE6Brochure.pdf

"Cray launches Gemini super interconnect", 25th May 2010
  http://www.theregister.co.uk/2010/05/25/cray_xe6_baker_gemini/
  http://www.theregister.co.uk/2010/05/25/cray_xe6_baker_gemini/page2.html
  http://www.theregister.co.uk/2010/05/25/cray_xe6_baker_gemini/page3.html


Gemini自体に HyperTransportの口がありますので、Opteronとは下のように
ダイレクトに接続出来ます (現行 SeaStar系も同様)

The architecture of the Cray Gemini interconnect
  http://regmedia.co.uk/2010/05/24/cray_gemini_architecture.jpg
実装 (Opteron 8ソケット、DDR3 x 4/ソケット＋ Gemini x 2)
  http://regmedia.co.uk/2010/05/24/cray_xe6_blade_server.jpg
※大きさは Opteronソケットから推測して下さい。


Cray XT4の演算ボードを見せた時 (もう XT4の Brochureが無い・・・)、

「"チップセット" はボードの裏ですか？」

と良く聞かれましたが、(多分、絶対)、XE6も実装は片面だけのはずです。