Reprints from my posting to SAN-Tech Mailing List and ...


[san-tech][03372] IBM 100 petaOPS Supercomputer出願特許公開、September 8, 2011

Date: Sat, 17 Sep 2011 14:07:59 +0900
IBMが 2011年 1月 10日に出願した特許書類が、2011年 9月 8日に公開され
ました (特許成立ではありません):

United States Patent Application: 20110219208
Kind Code: A1
Inventors: Asaad; Sameh ; et al.
Assignee: International Business Machines Corporation
Publication Date: September 8, 2011
Filed Date: January 10, 2011
※↑The United States Patent and Trademark Office (USPTO)

ブラウザー (Chrome) との相性問題か、分量の問題かで上手くいきません。
※A4 (Letter?) で、649枚です。460枚程度は図表です。
※後述する民間サイトでも PDFファイルを入手出来ますが、画像 PDFなので
単語検索出来ません。上記 URLはフラット HTMLです (ただし読み難い)。

"A Multi-Petascale Highly Efficient Parallel Supercomputer of
 100 petaOPS-scale computing, at decreased cost, power and footprint,
 and that allows for a maximum packaging density of processing nodes
 from an interconnect point of view. The Supercomputer exploits
 technological advances in VLSI that enables a computing model where
 many processors can be integrated into a single Application Specific
 Integrated Circuit (ASIC). Each ASIC computing node comprises
 a system-on-chip ASIC utilizing four or more processors integrated
 into one die, with each having full access to all system resources
 and enabling adaptive partitioning of the processors to functions
 such as compute or messaging I/O on an application by application
 basis, and preferably, enable adaptive partitioning of functions
 in accordance with various algorithmic phases within an application,
 or if I/O or other processors are underutilized, then can participate
 in computation or communication nodes are interconnected by a five
 dimensional torus network with DMA that optimally maximize
 the throughput of packet communications between nodes and minimize


SUMMARY (ほんの一部)
"A novel massively parallel supercomputer capable of achieving 107 petaflop
 with up to 8,388,608 cores, or 524,288 nodes, or 512 racks is provided.
 It is based upon System-On-a-Chip technology, where each processing node
 comprises a single Application Specific Integrated Circuit (ASIC).
 The ASIC nodes are interconnected by a five-dimensional torus networks
 that optimally maximize packet communications throughput and minimize
 latency. The 5-D network includes a DMA (direct memory access) network

以下に Description項目の大部分とほんの一部の引用を列記しますが、正直
ザッと目を通して感じでは、特許文章というより、BlueGene/Q (出願書類でも
明記) の仕様資料に感じます。また CPU構成等、最新 Supercomputerの教科書
にも良いかもしれません (ただし、かなりのバックグランドが要求されます)。
※これを基に図面を整理して、IBM RedBooksで BleGene/Q解説書として提供

Description (大部分の項目とほんの一部の引用)
  SUMMARY (上の引用はほんの一部だけ)
    "The present invention is directed to a next-generation massively
     parallel supercomputer, hereinafter referred to as "BluGene"
     or "BluGene/Q"."
  Compute ASIC Node
  I/O Node
  Memory Hierarchy-L1 and L1P (かなりの分量)
  Look-Up Engine
  Hit Queue
  Prefetch Data Array
  Prefetch Directory
  Look-Up and Stream Comparators
  LIST Prefetch Comparators
  Automatic Stream Detection, Manual Stream Touch
  Prefetch-to-Demand-Fetch Conversion Engine
  ECC and Parity
  Processing Unit (かなりの分量)
  L2 Cache
  Memory Synchronization Unit
  Levels of Synchronization
  Full Sync
  Non-Cumulative Barrier
  Producer Sync
  Generation Change Sync
  Producer Generation Change Sync
  Consumer Sync
  Memory Synchronization Interface Unit
  Full Sync
  Non-Cumulative Barrier
  Producer Sync
  Generation Change Sync
  Producer Generation Change Sync
  Consumer Sync
  Local Barrier
  Physical Design
  Software Interface
  Long and Short Running Speculation
  L1/L1P Hit Race Condition
  Speculation Model
  Multithreading Model
  Speculation IDs
  Life Cycle of a Speculation ID
  L2 as Point of Coherence
  ID Ordering for Speculative Execution
  Speculation ID Reclaim
  Transactional Memory
  Mode Switching
  Memory Consistency
  Commit Race Window Handling
  Transition to Committed State
  Thread ID Counters
  Conflict Handling
  Conflict Recording
  Conflict Detection
  TLS/TM/Rollback Management
  Global Speculation ID Management
  Processor Local Configuration
  Atomic Operations (かなりの分量)
  Miscellaneous Memory-Mapped Devices
  System Packaging
  System Interconnect-Five Dimensional Torus
  Packet Header and Routing
  Interrupt Control
  Network Support for System Initiated Checkpoint
  Mode Changes
  Multiple Tag Domains
  Integer Operations
  Floating Point Operations
  Floating Point (FP) Min and Max
  Floating Point ADD
  Global Clock
  Using Reproducibility to Debug a Multiprocessor System
  Aspects Allowing a Multiprocessor System to Offer Reproducibility
  Deterministic System Start State
  A Single System Clock
  System-Wide Phase Alignment
  System-Wide Synchronization Events
  Reproducibility of Component Execution
  Deterministic Chip Interfaces
  Precise Stopping of System State
  Scanning of System State
  Recording the Chronologically Exact Hardware Behavior (かなりの分量)
    "Blue Gene/Q racks are indirect water cooled."
  Power Distribution
  Power Management
  System Software
  Systems Software Overview
  Light Weight-Kernel

上記解説記事 (非常にコンパクトにまとめてあります)
"IBM Patent Filing Details First 100 PFlop Computer"
 September 09, 2011, ConceivablyTech

関連記事 (主として BlueGene/Qプロセッサの解説)
"IBM's BlueGene/Q super chip grows 18th core"
 It's nice to have a spare
 22nd August 2011, The Register

"Hot Chips 23 - IBMがスパコンエンジンのBlue Gene/Qチップを発表"
 2011/09/08, レポート、マイコミジャーナル

 2011/09/05, レポート、マイコミジャーナル


 富士通(株) 追永勇次

該当申請資料 URL

以前は登録しないと PDFファイル入手は不可だったと思いますが、

会社等からのアクセスは、個人的にはお勧めしません (それを言い出したら
USPTOはどうなの? ですが・・・)。

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