[san-tech][03544] Slide/Paper: TACC-Intel Highly Parallel Computing Symposium (2012/04/10, 11)

Date: Wed, 02 May 2012 12:47:12 +0900
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2012年 4月 10, 11日に TACC (Texas Advanced Computing Center) で
開催された、Intel MIC (Many Integrated Core) 関連シンポジウム：

TACC-Intel Highly Parallel Computing Symposium
 April 10th-11th, 2012
  http://www.tacc.utexas.edu/ti-hpcs12

の Slide/Paperが公開されています。

Program
  http://www.tacc.utexas.edu/ti-hpcs12/program

Invited Talks
Paper Session 1: "Early MIC Programming Experiences, Part 1"
Paper Session 2: "Early MIC Programming Experiences, Part 2"
Paper Session 3: "Performance and Communications on SCC"
Intel Video Presentation: "The Many Core Journey" (資料公開無し)
Poster Session: (資料公開無し)
Invited Talks
Paper Session 4: "Software Tools for MIC"


解説記事：
"TACC-Intel Symposium Highlights MIC Architecture Developments"
 May 01, 2012, HPCwire
  http://www.hpcwire.com/hpcwire/2012-05-01/tacc-intel_symposium_highlights_mic_architecture_developments.html?page=1


TACCでは Intel MICを採用する次期スーパーコンピュータの研究・構築が
進められています：

""Stampede's" Comprehensive Capabilities to Bolster U.S. Open Science
 Computational Resources"
 Texas Advanced Computing Center's new supercomputer to enable
 traditional HPC, data-intensive computing, and scientific visualization
 for nation's scientists
 September 22, 2011
  http://www.tacc.utexas.edu/news/press-releases/2011/stampede
.....
  "The new system, called Stampede, will be built by TACC in partnership
   with Dell and Intel ... NSF is providing $27.5 million immediately
   and Stampede is expected to be up and running in January 2013.
   The estimated investment will be more than $50 million over four
   years; ..."
.....
  "When completed, Stampede will comprise several thousand Dell "Zeus"
   servers with each server having dual 8-core processors from
   the forthcoming Intel Xeon Processor E5 Family (formerly codenamed
   "Sandy Bridge-EP") and each server with 32 gigabytes of memory. This
   production system will offer almost 2 petaflops of peak performance,
   ... The cluster will also include a new innovative capability: Intel
   Many Integrated Core (MIC) co-processors codenamed "Knights Corner,"
   providing an additional 8 petaflops of performance. ..."


Larrabee時代からの MIC関連資料 (URL) は以下にまとめています：
[Links]: Intel Many Integrated Core (MIC) Related Web Page